AGENDA

NOV 30, 2023

TIME PST TITLE SPEAKER(S)
08:00 AM
08:15 AM
Opening Keynote
Prith Banerjee
Chief Technology Officer, Ansys
08:15 AM
08:35 AM
Chiplets – How does EDA Eco System Need To Evolve?
Lalitha Immaneni
Vice President, Intel
08:35 AM
09:05 AM
Technology Innovation Panel – SigmaDVD: Breakthrough Technology Redefining Power Integrity
Ed Sperling
Editor-in-Chief, SemiEngineering
Chip Stratakos
Partner, Physical Design, Microsoft
Mohit Jain
Principal Engineer, Qualcomm
Murat Becer
Vice President, Ansys
Thomas Quan
Director, TSMC
09:05 AM
09:15 AM
Technology Keynote: 3D Thermal Challenges and the Way Forward
Murat Becer
Vice President, Ansys
09:15 AM
09:45 AM
SigmaDVD: Enabling breakthrough methodologies for IR prevention, analysis coverage, and accelerated design closure
Chip Stratakos
Partner, Physical Design, Microsoft
09:15 AM
09:45 AM
Novel CAD Methodology for IR Drop and Reliability Verification of Stacked Dies (3D-IC)
Matthew Jastrzebski
Engineer, Intel Corporation
09:15 AM
09:45 AM
High-Performance Design with Rapid RTL Profiling of Critical Power Scenarios
Alexander Pivovarov
SMTS, AMD
09:15 AM
09:45 AM
A Novel approach to cost-Efficient Hybrid Cloud Solutions with SeaScape's DataLake and Micro-Resiliency
Mohit Srivastava
Staff Engineer
09:15 AM
09:45 AM
Laying the Foundations for Optical Pass-Through Links’ Design
Luca Ramini
Research Scientist, Hewlett Packard Labs
09:15 AM
09:45 AM
ML-Based Multiphysics OptimizationsFrom Concept to Applications
Jerome Toublanc
Business Development executive
09:15 AM
09:45 AM
A Multiphysics Simulation Flow for High Performance MMIC Products for 5G and RF Applications
Vittorio Cuoco
Senior Principal Modeling Engineer - Multiphysics Simulations Competence Manager, Ampelon
09:15 AM
09:45 AM
A Novel Methodology for EM/IR analysis of Complex LDO/Power Gated Designs
Pavan Bilekallu
Lead Engineer, Layout, Qualcomm India Pvt. Ltd.
09:15 AM
09:45 AM
Accuracy and Performance benchmarks for Gate-level Power Integrity Signoff with RedHawk-SC Advanced Power Analytics
Love Gupta
Principal Design Engineer, NXP
09:45 AM
10:15 AM
Optimizing Power MOSFET Design with optiSLang AI/ML and Ansys Totem PMIC Utility
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
09:45 AM
10:15 AM
Early IR Drop Prediction Using Machine Learning for Power Grid
Anil D'Souza
CAD Engineer, Intel Technology Pvt Ltd
09:45 AM
10:15 AM
Silicon Interposer Extraction Using Ansys RaptorX
Garth Sundberg
Senior Principal Engineer, Ansys
09:45 AM
10:15 AM
SigmaDVD: High Coverage Solution for Power Integrity Signoff
Anusha Vemuri
Physical Design Methodology Engineer, NVIDIA
09:45 AM
10:15 AM
Optimizing Ansys Redhawk-SC with AMD Over InfiniBand Interconnect
Andy Chan
Lead, Microsoft Semiconductor Community, Microsoft
09:45 AM
10:15 AM
A Comprehensive Thermal Solution in Advanced Large Scale 3DIC Design
Ping Ding
Backend Designeer, Sanechips
09:45 AM
10:15 AM
Tracking Power Trends and Optimizations using PowerArtist and Actual Graphics Workloads
Sandesh Saokar
Graphics Hardware Engineer, Intel
09:45 AM
10:15 AM
Leveraging Scan Vectorless for ATPG Robustness
Mohit Jain
Principal Engineer, Qualcomm
09:45 AM
10:15 AM
Revolutionizing Chip Design: Python-Powered Workflow with Gdsfactory and Lumerical-Ansys Integration"
Joaquin Matres
Photonics Engineer, Google X
10:15 AM
10:45 AM
Optimizing Power MOSFET Design with optiSLang AI/ML and Ansys Totem PMIC Utility
Mandar Deshpande
Technical Staff Engineer, CAD, Microchip Technology Inc.
10:15 AM
10:45 AM
Revolutionizing Chip Design: Python-Powered Workflow with Gdsfactory and Lumerical-Ansys Integration"
Joaquin Matres
Photonics Engineer, Google X
10:15 AM
10:45 AM
Simulation Driven Enhancements to Photonic Integrated Circuit Devices in Tower’s PH18 Platform
Bowen Wang
Sr Staff, Tower Semiconductor
10:15 AM
10:45 AM
Synopsys/Ansys/Keysight RF Reference Design Flow on TSMC Advanced N4P Process
Marc Swinnen
Senior Principal Product Marketing Manager, Ansys
Keith Lanier
Technical Product Mgmt Director, Synopsys
10:15 AM
10:45 AM
Silicon Interposer Extraction Using Ansys RaptorX
Garth Sundberg
Senior Principal Engineer, Ansys
10:15 AM
10:45 AM
SPICE Validation of Dynamic Voltage Drops from SigmaDVD
Andy Hoover
Senior Principal Technologist
10:15 AM
10:45 AM
Thermal Aware Vectorless EM/IR Sign-off for Custom-IPs
Ayan Roy Chowdhury
Engineering Manager, Intel Technology India
10:15 AM
10:45 AM
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
10:15 AM
10:45 AM
Accuracy and Performance benchmarks for Gate-level Power Integrity Signoff with RedHawk-SC Advanced Power Analytics
Love Gupta
Principal Design Engineer, NXP
10:45 AM
11:15 AM
EMA3D Charge
Timothy McDonald
President, EMA
10:45 AM
11:15 AM
Novel Hierarchical IREM Sign-off Flow Using ROM
Dongyoun Yi
Staff Engineer, Samsung Electronics
10:45 AM
11:15 AM
Innovating Semiconductor Design with Ansys applications on AWS
Dnyanesh Digraskar
Principal HPC Partner Solutions Architect, AWS
10:45 AM
11:15 AM
EPDA: Bringing Layout Awareness to Photonics Simulation
Gilles LAMANT
Distinguished Engineer, Cadence Design Systems Inc
10:45 AM
11:15 AM
Early Clock Tree Power Correlation at SOC: A Case Study
Sri Sai Pavan Pasumarthi
Senior Engineer, Qualcomm
10:45 AM
11:15 AM
Integrated IR Shift-Left Solution in Construction in Fusion Compiler’s RedHawk Analysis Fusion (RAF)
Kiran Adhikari
Hardware Engineer, Microsoft Corporation
10:45 AM
11:15 AM
The tool certification process of Ansys RedHawk-SC Electrothermal: another successful collaboration with Ansys
Ki Wook Jung
Staff Engineer, Foundry Business, Samsung Electronics
11:15 AM
11:45 AM
3DIC Compiler & RHSC ET
Kenneth Larsen
Director of Product Management and Marketing
11:15 AM
11:45 AM
A Virtual Prototyping System for Silicon Carbide Power Modules
James Victory
Fellow, onsemi
11:15 AM
11:45 AM
An Accurate System-level Transient Droop Analysis Methodology for High Performance GPGPU Power Delivery Network
Yuanyuan Ling
Power Integrity Engineer, Iluvatar
11:15 AM
11:45 AM
Aggressor Aware Design for Improved IR-Drop Results
Vlad Berlin
Physical Design Engineer, Retym

Hora

17:00 - 18:00 hs GMT+1

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